IEEE EDS DU

Promoting excellence in research and learning in the area of electron devices

Promoting excellence in research and learning in the area of electron devices

Publications

Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation

Abstract: A novel design of a hybrid Full Adder (FA) using Pass Transistors (PTs), Transmission Gates (TGs) and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic is presented. Performance analysis of the circuit has been conducted using Cadence toolset. For comparative analysis, the performance parameters have been compared with twenty existing FA circuits. The proposed FA …

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Negative Capacitance Gate-All-Around Tunnel FETs for Highly Sensitive Label-Free Biosensors

Abstract: We propose a nanoscale, highly sensitive and label-free biosensor based on negative capacitance gateall-around tunnel field-effect transistor (NC-GAA-TFET). NC-GAA-TFETs provide steeper, sub-60 mV/dec subthreshold swing (SS) and higher drive current compared with the conventional gate-all-around tunnel field-effect transistor (GAA-TFETs). The combination of differential voltage amplification, due to the negative capacitance (NC) of the gate …

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Exploration of Negative Capacitance in Gate-All-Around Si Nanosheet Transistors

Abstract: Gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) are the most promising candidates to replace FinFETs and nanowire (NW) FETs in future technology nodes owing to their improved short-channeleffects, high current drivability per layout footprint (LF), and extreme scalability. The much-needed voltage scaling in these aggressively scaled devices can be provided by introducing negative capacitance …

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