IEEE EDS DU

Promoting excellence in research and learning in the area of electron devices

Promoting excellence in research and learning in the area of electron devices

The Physics of Negative Capacitance, its implementation in Ultra-thin Ferroelectrics and its implications for Next Generation Electronics

Title: The Physics of Negative Capacitance, its implementation in Ultra-thin Ferroelectrics and its implications for Next Generation Electronics

We are happy to announce that the IEEE EDS Student Branch Chapter, University of Dhaka, is going to  arrange a seminar on “The Physics of Negative Capacitance, its Implementation in Ultra-thin Ferroelectrics and its Implications for Next Generation Electronics” on the 24th of July, 2022. Your presence will be a great pleasure to us! The essential details about the session are provided below.

Abstract:

Mainly owing to the fundamental physics of the Boltzmann distribution, the ever-increasing power dissipation in nanoscale transistors threatens an end to the almost-four-decade-old cadence of continued performance improvement in complementary metal-oxide-semiconductor (CMOS) technology. It is now agreed that the introduction of new physics into the operation of field-effect transistors–in other words, “reinventing the transistor”– is required to avert such a bottleneck. In such a situation, a novel physical phenomenon called the negative capacitance effect in ferroelectric oxides was introduced. This phenomenon could dramatically reduce power dissipation in nanoscale transistors. The ongoing scaling of CMOS technology is now reaching its limit due to supply voltage reduction being restricted by the subthreshold swing (SS) of 60mV/decade achievable at room temperature owing to Boltzmann transport of the charge carriers. The concept of negative capacitance, proposed to achieve a sub-60mV/decade SS, is currently seen as one of the potential solutions to the problem. A “negative capacitance transistor (NCFET)” employs a ferroelectric material in the gate stack of a FET, providing a negative capacitance and thereby an “internal voltage amplification” at the gate of the internal FET, which helps in reducing SS. For this reason, it is becoming the dominant element for ultra-low power computing.

Details about the Session:

Date:  Sunday, 24 July 2022

Time:  2:30 P.M. (BST)

Type: Offline

Venue: 

Room#208, 1st Floor

Department of Electrical and Electronic Engineering

University of Dhaka, Dhaka-1000

Bangladesh.

The session is free to all.

For any query, e-mail us at ieeeedssbcdu@gmail.com.

Speaker Biography:

Sayeef Salahuddin is the TSMC Distinguished Professor of Electrical Engineering and Computer Sciences at the University of California Berkeley. Salahuddin received his B.Sc. in Electrical and Electronic Engineering from BUET (Bangladesh University of Engineering and Technology) in 2003 and his PhD in Electrical and Computer Engineering from Purdue University in 2007. He joined the faculty of Electrical Engineering and Computer Science at the University of California, Berkeley in 2008.

His work has focused on the conceptualization and exploration of novel device physics for low power electronic and spintronic devices. Salahuddin has championed the concept of using ‘interacting systems’ for switching, showing the fundamental advantage of such systems over the conventional devices in terms of power dissipation. This led to the discovery of Negative Capacitance Transistors that allow for sub kT/q subthreshold operation in transistors.

 

 

Salahuddin has received the Presidential Early Career Award for Scientists and Engineers (PECASE), the highest honor bestowed by the US government on early career scientists and engineers. Salahuddin also received a number of other awards, including the NSF CAREER award, the IEEE Nanotechnology Early Career Award, the Young Investigator Awards from the Air Force Office of Scientific Research (AFOSR) and the Army Research Office (ARO), and best paper awards from IEEE Transactions on VLSI Systems and from the VLSI-TSA conference. In 2012, Applied Physics Letters (APL) highlighted two of his papers among the 50 most notable papers among all areas published in APL within 2009-2012. Salahuddin also received the George E. Smith Award from the IEEE Electron Devices Society.

Salahuddin is a co-director of the Berkeley Device Modeling Center and the Berkeley Center for Negative Capacitance Transistors. He served on the editorial board of IEEE Electron Devices Letters (2013-16) and was the chair of the IEEE Electron Devices Society committee on Nanotechnology (2014-16).

Salahuddin is a fellow of the IEEE and the APS.