Promoting excellence in research and learning in the area of electron devices

Promoting excellence in research and learning in the area of electron devices

Modeling and Simulation of Negative Capacitance Transistors

Title: Modeling and Simulation of Negative Capacitance Transistors


You have surely heard of ‘Negative Capacitance’ or the word ‘NCFET’ in your electronic ventures, but maybe you don’t know exactly how to visualize it (NCFET) in a computer based software. If this is the case, don’t worry! IEEE EDS SB DU is now on its way to present its flagship event on this topic. This online session will be free of charge! What are you waiting for? Register now and get the link to join the event and satisfy your thirst for knowledge!

Mainly owing to the fundamental physics of the Boltzmann distribution, the ever-increasing power dissipation in nanoscale transistors threatens an end to the almost-four-decade-old cadence of continued performance improvement in complementary metal-oxide-semiconductor (CMOS) technology. It is now agreed that the introduction of new physics into the operation of field-effect transistors–in other words, “reinventing the transistor”– is required to avert such a bottleneck. In such a situation, a novel physical phenomenon called the negative capacitance effect in ferroelectric oxides was introduced. This phenomenon could dramatically reduce power dissipation in nanoscale transistors. It was theoretically proposed in 2008 that by introducing a ferroelectric negative capacitance material into the gate oxide of a metal-oxide-semiconductor field-effect transistor (MOSFET), the subthreshold slope could be reduced below the fundamental Boltzmann limit of 60 mV/dec, which, in turn, could arbitrarily lower the power supply voltage and the power dissipation. For this reason, it is becoming the prominent element for ultra-low power computing.

Details about the Webinar:

Registration Link:

Deadline of Registration: Sunday, 11 August 2021; 5:00  P.M. (BST) / 4:30 P.M. (IST) 

Date: Wednesday, 11 August 2021

Time: 6:30 P.M. (BST) / 6:00 P.M. (IST)

Type: Online

Platform: Zoom

Zoom Link: A zoom link will be provided to the registered participants.

For any query, e-mail us at


Abstract of the Talk: 

The ongoing scaling of CMOS technology is now reaching its limit, due to supply voltage reduction being restricted by the subthreshold swing (SS) of 60mV/decade achievable at room temperature owing to Boltzmann transport of the charge carriers. Concept of negative capacitance proposed to achieve a sub-60mV/decade SS is currently seen as one of the potential solutions to the problem. A “negative capacitance transistor (NCFET)” employs a ferroelectric material in the gate stack of a FET providing a negative capacitance and thereby an “internal voltage amplification” at the gate of the internal FET which helps in reducing SS. Several experiments have successfully demonstrated an improved SS with the bulk MOSFET, FinFET, and 2D FETs. The improvement in subthreshold characteristics is also accompanied with the advantage of an increased ON current relative to the reference FET as has been observed both in simulation studies and experiments. In this talk, our honorable speaker will discuss the physics and modeling of various NCFET structures and impact of this new transistor on circuits including processors.


Yogesh Singh Chauhan

Faculty Member, Department of Electrical Engineering, Indian Institute of Technology, Kanpur, Kanpur, U.P. – 208016, India.

Speaker Biography:

Yogesh Singh Chauhan is a professor at Indian Institute of Technology, Kanpur, India. He was with Semiconductor Research & Development Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012; and STMicroelectronics during 2003-2004. He is the developer of several industry standard models: ASM-GaN-HEMT model, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are characterization, modeling, and simulation of semiconductor devices.  

He is the Fellow of IEEE, Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is a member of IEEE-EDS Compact Modeling Committee and a fellow of Indian National Young Academy of Science (INYAS). He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and Vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences.

He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award, Humboldt fellowship and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.